the m29320 provides a complete physical-layer solution for flexible high-bandwidth ds3/e3 services, including secure private leased lines and video conferencing. the m29320 replaces up to 3 discrete devices, enabling cost- effective ds3/e3 services to be deployed in both new and existing platforms. the m29320 includes 12 independent ds3/e3/sts-1e elec- trical line interface units (lius) with built-in digital jitter attenuators (djat), 24 ds3/e3 framers (12x in receive and 12x in transmit for monitoring only), and 12 sts-1 framers. each port is capable of supporting ds3/e3/sts-1e mapped/demapped signals to/from sonet/sdh interface. the m29320 line side interfaces support electrical ds3/e3/sts-1e, requiring only the addition of trans- formers and passive termination. the m29320 system interface supports sts-12/stm-4 for the sonet/sdh traffic via dual high speed serial lvds (622 mbps) interfaces as active and protect, or a standard 8-bit, 77 mhz tdm telecom bus. granularity of service is an important feature of this device. it can take a channelized oc-12 connection and break it all the way down to ds3/e3 streams. densely channelized oc-12 line cards, enabled by the m29320, are becoming enormously popular at the edge of the network as carriers backhaul all their traffic to an access point-of-presence (pop) where they will terminate the customer traffic in an edge router or multiservice switch before transporting it onto the internet sonet/sdh backbone. the m29320 integrates 12 ds3/e3/sts-1e mapper/ framers, with corresponding field-proven desynchronizers using dsp technology (djat) and an sts-12/stm-4 sonet/sdh framer, to support ds3/e3/sts-1e mapping into sonet/sdh on a channel-by-channel basis. this allows adms/oeds and mspps to deploy a single line card that supports the simultaneous mapping and transport of both ds3 and e3, which is significant for european and asian carriers as their networks have a mix of ds3 and e3 that must be transported across their sdh infrastructure. > high-density - 12 ds3/e3/sts-1 lius with jitter attenuation/ desynchronization > 24 ds3/e3 framers > 12 ds3/e3 mappers/ demappers > 12 sts-1 sonet/sdh framers > sts-12/stm-4 sonet/sdh tdm framer > parallel 8-bit, 77.76 mhz tdm telecom bus > dual high speed serial lvds 622 mhz interface > dual embedded oc-12 cdrs > > key features 12-port ds3/e3/sts-1 electrical integrated line termination device for transport networks m29320 - single chip solution
www.mindspeed.com/salesoffices general information: (949) 579-3000 headquarters C newport beach 4000 macarthur blvd., east tower newport beach, ca 92660-3007 29320-BRF-001-A m03-0789 ? 2003 mindspeed technologies ? . all rights reserved. mindspeed and the mindspeed logo are trademarks of mindspeed technologies. all other trademarks are the property of their respective owners. although mindspeed technologies strives for accuracy in all its publications, this material may contain errors or omissions and is subject to change without notice. this material is provided as is and without any express or implied warranties, including merchantability, fitness for a particular purpose and non- infringement. mindspeed technologies shall not be liable for any special, indirect, inci- dental or consequential damages as a result of its use. ? 12 ds3/e3/sts-1e lius with jitter attenuation/desynchronization - fully adaptive receive equalizer enables greater than 1800 ft of cable reach - fully programmable transmit pulse mask configuration - dynamic loop bandwidth to comply with all sonet and bell core intrinsic and output jitter requirements ? 24 ds3/e3 framers support ds3- m13, ds3-m23, ds3 c-bit parity e3- g.751, e3-g.832 ? 12 ds3/e3 mappers/demappers supporting ds3/vc-3/au-3; ds3/tug-3/au-4; e3/vc-3/au-3; e3/tug-3/au-4 ? 12 sts-1 sonet/sdh framers support transport overhead access; includes monitor and generator ? sts-12/stm-4 sonet/sdh tdm supporting mapping/demapping of 12 sts-1e or au-3 into/from sts- 12/stm-4 frame - pointer processing - transport overhead insertion and extraction - parallel 77.76 mhz x 8-bit telecom bus interface - dual serial lvds 622 mhz bus interface with embedded cdr with support for no-bit-loss switching ? synchronous 16-bit microprocessor interface bus at 30C77 mhz bus rate ? local (source) and remote (line) loopback capability at various internal points in the device ? prbs detector and generator supporting framed and unframed modes ? jtag (ieee 1149.1) boundary scan ? single rail 1.8 v core supply with 3.3 v lvttl i/o, 1.8v lvds i/o ? embedded clads internally gener- ating the three line rate (ds3/e3/sts-1) clocks applications ? adm/oeds ? dslam & ngdlc ? digital access cross-connect systems product features in addition, the m29320 supports pseudo-random bit sequence testing, and a full set of loopback functions are provided at different functional blocks. the m29320 requires only one 19.44 mhz reference clock (passive crystal) or seven 7.76/155.52 mhz sonet reference clocks for gener- ating all the necessary internal line rate clocks and enabling the same reference clock to be available on an output pad. the m29320 is offered in a 35mm fcbga package. microprocessor interface oc-12 mux/ demux mini- framer and built-in cdr 12x ds3/e3 to sts-1e mapper/ demapper 24x ds3/e3 framers 12x ds3/e3 or sts-1e liu + djat oh access 12 lines ds3/e3/ sts-1e (ec-1) m29320 12x sts-1 framers prbs generator and monitor jtag sts-12 active sts-12 protected telecorn bus lines test i/f sts-1 overhead access systems control sts-12 overhead access 622 mhz active lvds 622 mhz protected lvds 8-bit 77 mhz m29320 functional block diagram
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